Embedded Insight Archives
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The Ubiquitous 8051
Back in 1980, Intel introduced the first 8051 microcontroller. Today in 2002, the 8-bit 8051 is still very popular with a cornucopia of choices available from multiple vendors. We'll explore some of the features of this microcontroller family so you can get a sense of its capabilities.
The 8051 is based on a Harvard architecture where there are separate logical spaces for program memory and data memory. This helps to simplify the hardware design somewhat but can make the software a little trickier. The original 8051 had the following features:
Of course, with all the new derivatives, there are various improvements and additional peripherals tailored for every design including:
One of the biggest improvements to performance is the number of clock cycles necessary for each instruction. The original 8051 needed 12 clock cycles per instruction. Thus, at 12 MHz, you got 1 MIPS (Millions of Instructions Per Second, not VAX MIPS or Dhrystone MIPS). Dallas Semiconductor (now part of Maxim Integrated Products) came out with a derivative many years ago that only needs 4 cycles per instruction. This results in a speed improvement of up to 3X! Philips Semiconductor has models that only need 6 cycles per instruction, a 2X improvement. (The actual improvement times will vary somewhat because instruction timing has changed in addition to the cycles per instruction.)
The 8051 has the following registers:
All registers are accessed through Special Function Registers (SFRs) except for the PC. SFRs are accessed in the low addresses of data space. All peripherals like a timer or UART are also accessed via SFRs. In the new derivatives, the original SFRs are left at their original addresses for software compatibility. The memory maps for all 8051 devices are really close to the original 8051. For reference, here is a memory map for the SFRs of the original 8051.
Diagram 1: Original 8051 SFR memory map
For comparison, here is the memory map for the SFRs of a newer more highly integrated chip with many more peripherals, the Philips P8xCE558. Note that all of the original SFRs are at the same addresses. The new SFRs handle new peripherals and features such as an ADC, PLL, PWM outputs, a second UART, additional I/O ports, and additional interrupts.
Diagram 2: Philips P8xCE558 SFR memory map
One of the coolest features of the 8051 is bit addressing. Bit addressing allows a single bit to be read or written with a single instruction. While this is no real big feat, there is an area of RAM from address 0x20 to 0x2F that is bit-addressable (bit addresses 0x00 to 0x7F). This translates into 128 1-bit variables or flags accessible from C code. Normally, when a C programmer creates flags, you use a declaration such as:
where the value of fGlobalFlag will only ever be 0 or 1. Using an 8-bit variable to store a 1-bit variable is just a waste of space, so many 8051 compilers add a keyword to allow bit-addressable variables:
All SFRs with an address ending in 0 or 8 are also bit addressable, so it's really easy to enable/disable features and flip bits even in assembly language.
When an interrupt occurs, the program pointer is set to the appropriate interrupt vector. At each interrupt vector is 8 bytes of program space, usually enough space to handle the interrupt or set a flag. This leads to highly efficient interrupt handling if it is feasible to keep the interrupt routines short. Of course, if your ISR is more complex, a jump instruction can be placed there as well.
There are four register banks available which switch between different copies of R0 through R7. This allows easy context switches without having to save registers. The most obvious example is the handling of interrupts. Suppose we have an 8051 system where interrupts of both low and high priorities are enabled. We could handle the ISRs by assigning different register banks for each interrupt priority level as follows:
Thus, when an interrupt occurs, a bank switch is all that's necessary to preserve and restore registers.
As you may have noticed, the SP is only 8 bits in size. This means that the stack must reside in internal RAM. Moreover, the maximum stack size is 248 bytes if we only use one register bank (not a realistic option). So how do we implement a larger stack?
On the one hand, you may not need a very large stack. In most 8051 systems, function parameters are not pushed on the stack. Parameters are passed in registers first, then in a function-specific parameter area in RAM so that the stack only contains return addresses for subroutines. The only things on the stack are return addresses for subroutines. One major side effect of this implementation is that recursion is not possible.
On the other hand, if you absolutely must have a large stack or implement a recursive algorithm, most development environments have an option to place the stack in external memory. This is a software-maintained stack and is much slower than the native stack operations. Another option is to find a new derivative with a larger stack pointer. For example, Philips has what they call the 51MX core (Memory eXtension) which has a 16-bit SP giving you access to almost 64 KB of stack space.
One of the limitations of the original 8051 is a 64 KB addressing space in program and data spaces (128 KB total). Fortunately, most of today's compilers allow a bank-switched memory model which gives the programmer access to almost unlimited space.
At least one vendor has introduced an extended address bus. The Philips 51MX core can access 8 MB each of program and data memory. They have increased the PC and Data Pointers to 23 bits each to eliminate the need for a software paging mechanism.
At over 20 years old, the 8051 is a very mature microcontroller family. There are many vendors for chips, tools, operating systems, and even processor cores for your microcontroller ASIC. While we can't possibly list all the vendors of 8051 goods here, the following is a sampling of what's out there.
Compilers and Debuggers
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